VRAMpage MD

v0.5.1 experimental

Mega Drive memory experiments. Model 1 logical fault models.

CORE NOT READY

01 / Game

MODEL 1 · NTSC-U · 59.92 Hz
NO CARTRIDGE

Choose a built-in cartridge or load your own ROM. The emulator runs entirely in your browser.

NO CARTRIDGE INSERTED— FPS
Video: native pixels
Checking Region Support…

PLAY Arrows / Z X C / Enter | FAULTS 1–9 toggle / Shift+1–9 hold / 0 next chip / P pause

05 / Logic / SRAM (Work RAM)

Experimental · 68000 Bus Model

Bridge one pair of modeled Work RAM lines. Apply a fault explicitly; the selectors do not activate it by themselves.

Work RAM switches. Address/Data wires force selected signals low using Access; data bridges stay within D0–D7 or D8–D15. Writes inhibits the lower (/LWR) or upper (/UWR) byte's future stores, retaining its old contents. Inhibit models an inactive/high write-enable input, not a floating cut. These RAM faults replace one another. The two-byte Model 1 reference and drawing show logical signals; real open wires can float.

CPU recovery disconnects Work RAM, VRAM and Z80 RAM faults, leaves PSG/FM faults unchanged, preserves corrupted RAM and may immediately stop again. CPU-only reset leaves other chips running. The Randomiser-row Force Resume and CPU Recovery switches start On. Two eligible HALT frames trigger one Force Resume; eight further HALT frames permit one CPU-only reset. Turning Force Resume Off skips directly to one CPU reset after two HALT frames. STOP alone does not trigger recovery. A new fault action, toggle change or explicit Resume permits another sequence. This does not detect software loops or a browser locked inside a frame. Disconnect All Faults pauses only when clearing a domain is unavailable, partial or unverified; Clean Restart fully reboots.

No Session Checkpoint

One checkpoint in this session only. Save with faults off and controls released. Restore clears faults and stays paused; press Resume when ready. Clean Restart or loading a cartridge discards the checkpoint. Unsupported cartridge profiles cannot use checkpoints.

Quick address pairs: write pulses, using the limit above. Each button applies a pair, then disconnects and attempts resume. These bridge address lines, not particular RAM locations. Affected-write limits release inside the core and expire after one frame. Even one affected write can disrupt later execution; small or recoverable corruption is not guaranteed.

Checking core support…

Affected Reads0
Affected Writes0
Current Frame0
Activation Frame—
CPU Status Flags—

Model limits. This is an experimental transaction model, not an exact physical pin or cycle-level simulation. Read faults affect returned values; write faults alter stored RAM and those changes persist after disconnecting. CPU STOP/HALT indicators report flags only; automatic HALT recovery follows the switches above. Turn both Off for unassisted experiments. Data pairs must stay within D0–D7 or D8–D15. VRAM and logic/Work RAM faults remain mutually exclusive; the Z80 RAM write bridge is independent.

06 / PSG Input Bridge

D0-D7

Bridge two PSG data inputs. If either requested bit is low, both bridged inputs are forced low on each future PSG write.

Checking core support…

PSG Data Writes0
Bytes Changed0

The counters aggregate at the PSG write sink and do not identify which CPU initiated a write. Disconnecting changes future writes only. The model does not repair current PSG chip state.

07 / FM Register Input Bridge

D0-D7

Bridge two FM data inputs. The selected low-dominant inputs are applied to each register-address and register-data byte before the chip decodes it.

Checking core support…

FM Register Writes0
Bytes Changed0

Counters aggregate at the shared FM write boundary and do not identify which CPU initiated a write. Removing the bridge affects future writes only; it does not repair current chip state. Full sound reset clears the bridge. Z80-only reset preserves the bridge connection and counters.

08 / Circuit Configuration

Versioned JSON

Save fault settings without ROM data or execution history. Loading a file only stages a preview; faults change only after you choose Apply.

No configuration staged.

09 / Compare Exports

Local · Read-Only

Load two experiment JSON exports to compare recorded identity, fault settings, counters and outcomes. Files are read in this browser only. Unknown values may be absent, invalid, or unavailable; long values are shortened. Comparison does not establish causal or gameplay equivalence.

Choose two exported experiment JSON files.

03 / Event Log

View Activity

    04 / Build Notes

    Technical Details

    Includes approved original homebrew cartridges. Your own cartridge files stay in this browser and are never uploaded.

    Sound is available with Enable Sound. The separate logic/Work RAM panel is an experimental 68000 transaction model.

    The game display automatically fills consistently missing framebuffer rows. Select Raw Emulator Output to inspect untouched pixels. This does not alter emulated VRAM or hardware faults.

    Emulator: wasm-genplus / Genesis Plus GX. Redistributing a modified core requires its corresponding source and applicable licence notices.